Computer Architectures for nanotech - ROM, 13/Mar/03


Recently people have had to worry about the consequences of moving software to 64-bit architectures from 32-bits; of course some people have been working on this since at least the early 1990s.

Do we have any ideas about:

a) The sort of architectures that will be needed to support nanotech; will 32-bit, 64-bit, 128-bit or whatever be required? Will 16-bits be enough?

b) What sort of architectures will nanotech reasonably make available to us, 64-bit, 256-bit, whatever? Presumably so as to be able to access massive storage?

I am ignoring here that massive parallelism and dynamic networking will almost certainly be involved, and looking at the basic computing processor.

Thoughts?


(c) Rory O. McLean, 1980 - Feb. 2006
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